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SpinalHDL is a Scala based internal DSL which allow describing and generating synthesizable VHDL/Verilog netlist.

This is a video by Andreas Wallner about "SpinalHDL Intro for New Users"

https://media.ccc.de/v/33c3-7873-spinalhdl_an_alternative_hardware_description_language Since too long we use VHDL and ...

Today's subject : Turn CODE into Hardware ‍ GITHUB for access to code & deeper material ...

In order to help people further understand SpinalHDL, DatanLord and SpinalHDL community held an online seminar (Webinar) ...

Presented by Charles Papon at WOSH - Week of Open Source Hardware SpinalHDL was initially made to be a good alternative to ...

Bluespec: https://github.com/B-Lang-org/bsc Chisel: https://www.chisel-lang.org Support this channel via a special purpose ...

https://fpga.pulserain.com/2023/03/limerick4-linter-formatter-logging-and.html *) Linter for C/C++ *) Formatter for C/C++ *) Linter ...

In order to help people further understand SpinalHDL, DatanLord and SpinalHDL community held an online seminar (Webinar) ...

by Charles Papon At: FOSDEM 2017 Since too long we use VHDL and Verilog to describe hardware. SpinalHDL is analternative ...

In order to help people further understand SpinalHDL, DatanLord and SpinalHDL community held an online seminar (Webinar) ...

The reason to choose SpinalHDL over VHDL/Verilog/SystemVerilog/Chisel.

FOSDEM 2017 Hacking conference #hacking, #hackers, #infosec, #opsec, #IT, #security.

This is a video of yportne13 about" Some Tips on Using Memory Black Box in SpinalHDL"

In order to help people further understand SpinalHDL, DatanLord and SpinalHDL community held an online seminar (Webinar) ...

Create a SaxonSoC and custom logic with SpinalHDL and get it running on an Efinix Xyloni demo board. Refer guithub for details.

What better way to learn about a new HDL than actually taking it for a spin, and creating something annoying?