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Algorithmic Level Techniques for Low Power Design
00:30:53
Summarization of the Course
00:14:38
Other Low Power Design Techniques
00:24:41
Gate Level Design for Low Power (Part 2)
00:31:26
Gate Level Design for Low Power (Part 1)
00:28:51
Techniques to Reduce Power
00:36:11
Low Power VLSI Design
00:32:30
Design for Testability
00:30:07
Test Pattern Generation
00:33:04
Boundary Scan Standard
00:28:28
Built-in Self-Test (Part 1)
00:30:51
Built-in Self-Test (Part 2)
00:23:02
Fault Modeling (Part 2)
00:29:09
Fault Modeling (Part 1)
00:34:17
Fault Simulation (Part 2)
00:34:23
Testing of VLSI Circuits
00:30:31
mod09lec50
00:29:09
Fault Simulation (Part 1)
00:28:48
Layout Compaction (Part 2)
00:33:49
Layout Compaction (Part 1)
00:24:38
Design Rule Check
00:28:38
Interconnect Modeling (Part 2)
00:32:17
Interconnect Modeling (Part 1)
00:32:33
Miscellaneous Approaches to Timing Optimization
00:32:19
Performance-Driven Design Flow
00:23:14
Physical Synthesis (Part 2)
00:30:44
Physical Synthesis (Part 1)
00:28:50
Timing Driven Routing
00:33:03
Timing Driven Placement
00:29:29
Time Closure (Part 1)
00:34:48